1. Field of the Invention
The present invention relates to a semiconductor device comprising at least two complementary type transistors formed around a heterostructure of junctions between materials of the III-V groups. One of the particular features of this device is that its structure can be used to balance the threshold voltages V.sub.T of the two transistors, which are n and p type transistors, and to optimize their mutual conductance or transconductance values, despite the differences in mobility between the electrons and the holes.
One of the objects of this device is to reduce the electrical consumption of the fast logic circuits and of the microwave circuits.
2. Description of the Prior Art
It is known that, in fast logic circuits, to date it is only n type transistors that are used because, in the channel, the electrons have far higher mobility than the holes, giving the transistors a higher cut-off frequency.
It is also known that the basic cell in logic circuits is the inverter, as shown in FIG. 1. This DCFL (Direct Coupled FET Logic) type inverter is formed by an enhanced n type input transistor 1, series-connected with a depleted n type active load 2, the entire unit being supplied between the ground and a voltage V.sub.DD. The input signal is applied at I on the gate of the transistor 1 and the output signal is collected at O on the drain of the same transistor. The power consumed (0.3, 1 mW) by this basic inverter: ##EQU1## is proportional to the working frequency (kf) but comprises a constant term corresponding to the consumption of the active load 2, even if the inverter is idle.
The use of a BFL (Buffered Fet Logic) inverter is even more characteristic for, apart from the fact that the transistors are all depletion transistors, the inverter of FIG. 1 is followed by a shifting stage which also consumes power in the idle state, which means that the power consumed is of the order of 5 to 10 mW.
Furthermore, it is known that complementary MOS transistors, on silicon, have the advantage of zero consumption when idle and have consumption proportional to the frequency (kf) when working. This is why, for fast logic systems (corresponding to operation at microwave frequencies in the gigahertz range), it is desirable to have a device comparable to MOS transistors, which are presently limited to about 1 to 3 GHz.
Circuits have been made on the basis of this principle, using two HIGFET (Heterostructure Insulated Gate Fet) transistors or heterostructure field-effect transistors, one of them with one n channel and the other with one p channel. The heterostructure (i.e., by definition, one or more junctions between two or more layers of different materials of the III-V group, for example GaAs and GaInAs) is promising because it is one of the bases (among others) of the fast transistors known as TEGFETs or HEMTs (High Electron Mobility Transistors) and because HIGFETs have an excellent uniformity of threshold voltage V.sub.T on a wafer, during manufacture. This threshold voltage depends very little on the temperature and shows little sensitivity to light because it is not controlled by dopants.
A first drawback of HIGFETs, in their known structures, is that the two transistors, n and p, have different threshold voltages, in terms of absolute value, which is not suited to logic operations since the logic pulses (the bits) must have the same amplitude irrespectively of the transistor that is in operation.
A second drawback of known HIGFETs is the difference in transconductance between the two channels which is of the order of 218 mS/mm for the n channel and 28 mS/mm for the p channel, at ambient temperature in both cases. This difference can be explained notably by the low mobility of the holes .mu..sub.h at ambient temperature.